1. Field of the Invention
The present invention relates to power supply circuits, and more particularly to digital control systems and methods for switched mode power supply circuits.
2. Description of Related Art
Switched mode power supplies are known in the art to convert an available direct current (DC) or alternating current (AC) level voltage to another DC level voltage. A buck converter is one particular type of switched mode power supply that provides a regulated DC output voltage to a load by selectively storing energy in an output inductor coupled to the load by switching the flow of current into the output inductor. It includes two power switches that are typically provided by MOSFET transistors. A filter capacitor coupled in parallel with the load reduces ripple of the output current. A pulse width modulation (PWM) control circuit is used to control the gating of the power switches in an alternating manner to control the flow of current in the output inductor. The PWM control circuit uses signals communicated via a feedback loop reflecting the output voltage and/or current level to adjust the duty cycle applied to the power switches in response to changing load conditions.
Conventional PWM control circuits are constructed using analog circuit components, such as operational amplifiers, comparators and passive components like resistors and capacitors for loop compensation, and some digital circuit components like logic gates and flip-flops. But, it is desirable to use entirely digital circuitry instead of the analog circuit components since digital circuitry takes up less physical space, draws less power, and allows the implementation of programmability features or adaptive control techniques. A conventional digital control circuit includes an analog-to-digital converter (ADC) that converts an error signal representing the difference between a signal to be controlled (e.g., output voltage (Vo)) and a reference into a digital signal having n bits. The digital control circuit uses the digital error signal to control a digital pulse width modulator, which provides control signals to the power switches having a duty cycle such that the output value of the power supply tracks the reference. In order to keep the complexity of the PWM control circuit low, it is desirable to hold the number of bits of the digital signal to a small number. At the same time, however, the number of bits of the digital signal needs to be sufficiently high to provide resolution good enough to secure precise control of the output value. Moreover, the ADC needs to be very fast to respond to changing load conditions. Current microprocessors exhibit supply current slew rates of up to 20 A/μs, and future microprocessors are expected to reach slew rates greater than 350 A/μs, thereby demanding extremely fast response by the power supply.
Single stage (i.e., flash) ADC topologies are utilized in power supply control circuit applications since they have very low latency (i.e., overall delay between input and output for a particular sample). If a standard flash ADC device is used to quantize the full range of regulator output voltage with desired resolution (e.g., 5 mV), the device will necessarily require a large number of comparators that will dissipate an undesirable amount of power. Under normal operation, the output voltage Vo of the regulator remains within a small window, which means that the ADC need not have a high resolution over the entire range. Accordingly, a “windowed” ADC topology permits high resolution over a relatively small voltage range tracked by a reference voltage (Vref). Since the quantization window tracks the reference voltage Vref, the signal produced by the ADC will be the voltage error signal. Thus, the windowed ADC provides the dual functions of the ADC and error amplifier, resulting in a further reduction of components and associated power dissipation.
Notwithstanding these advantages, a drawback with the windowed ADC topology is that the device can go into saturation due to transient load conditions that cause the window ranges to be exceeded. By way of example, a 4-bit windowed ADC has a least significant bit (LSB) resolution of roughly 5 mV. This means that an output voltage error of as low as ±40 mV pushes the ADC into saturation. The ADC would then continue to reflect the same error signal (i.e., maximum) even though the actual error could grow even larger, referred to as a “windup” condition of the digital control system. The reaction of the feedback loop in this windup condition can be difficult to predict, since without accurate information about the error size the digital control system no longer functions as a linear system. This behavior can be particularly harmful, since it can damage the load due to overcurrent and/or overvoltage, and can also damage the power supply itself.
Thus, it would be advantageous to provide a system and method for digitally controlling a switched mode power supply that overcomes these and other drawbacks of the prior art. More specifically, it would be advantageous to provide a system and method for digitally controlling a switched mode power supply having a windowed ADC topology that can maintain accurate voltage regulation during ADC saturation caused by transient load conditions.